Panasonic MN101L Series

Chapter 8
8-bit Timer
Overview VIII - 3
8.1.2 8-bit Timer Block Diagram
8-bit Timer block diagram is shown in Figure:8.1.1
Timer 0, Timer 2 and Timer 4 are described "Timer n", Timer 1, Timer 3 and Timer 5 are described "Timer m".
Figure:8.1.1 Block Diagram of Timer n and Timer m
M
U
X
M
U
X
M
U
X
M
U
X
HCLK
TMnIO
HCLK/16
HCLK/32
HCLK/64
SYSCLK/2
SYSCLK/4
SCLK
HCLK/4
HCLK
TMmIO
HCLK/16
HCLK/64
HCLK/128
SYSCLK/2
SYSCLK/8
SCLK
HCLK/4
TMmIRQ interru
pt
TMnIRQ interrup
t
TMnCK1-0 (TMnMD register)
TMnPSC1-0,TMnBAS (CKnMD register)
TMnOC register
TMnBC register
TMmOC register
TMmBC register
Overflow
matching detection
matching
detection
TMmCAS bit
(TMmMD register)
TMmCK1-0 (TMmMD register)
TMmPSC1-0,TMmBAS (CKmMD register)
Timer n output
generation
TMmIO outpu
t
TMnIO outpu
t
Timer m output
generation