Chapter 5
Watchdog Timer (WDT)
V - 2 Overview
5.1 Overview
The watchdog timer (WDT) generates NMI (WDIRQ) when the dedicated counter (WDT-Counter) is not cleared
during the error detect period and overflows. When two consecutive WDIRQs occur without clearing WDT-
Counter, the LSI is reset by hardware. The clock source of WDT-Counter is selected from SOSCCLK or SRC-
CLK.
The following table shows the relationship between CPU mode and the WDT operation when WDT is active.
WDT-Counter is initialized when the LSI is reset or is in STOP mode.
Table:5.1.1 Relationship between CPU mode and WDT operation
..
When the WDIRQ is generated, the LSI can be in unexpected state. Therefore appropriate
measures to make the LSI operate normally should be taken.
..
CPU mode WDT-Counter operation
NORMAL/IDLE/SLOW/HALT
Continue to count
* Count operation doesn’t stop even during the mode transition.
STOP
Stop counting (The value of WDT-Counter is cleared.)
* WDIRQ is not generated in STOP mode.
OSCCLK
WDT-Counter
WDCTR
Reset/Interrupt
control
LSI res
WDIRQ
Overflow
R
rite to WDCTR
SRCCLK
WDCTR.WDCKSEL
WDTCLK
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