Chapter 4
Clock/ Mode/ Voltage Control
Voltage Control IV - 29
4.3.4 Operation
Voltage Transition of VDD18 by Program
Figure:4.3.1 shows the example of voltage transition of VDD18 by program.
When SLOW mode, the PWCTR0.VDDLV1-0 are set to change the output voltage, VDD18 and achieve low-
power consumption or high-speed operation depending on the operating frequency.
Voltage transition cannot be set in NORMAL mode. It is also impossible to change the voltage from 1.3 V to 1.8
V and from 1.8 V to 1.3 V. After updating the PWCTR0.VDDLV1-0, CPU clock is halted for the time set in the
PWCTR1.PWUPTM2-0 while the voltage is boosted during i) and iii) shown in the Figure:4.3.1. Although CPU
clock is not halted while the voltage is stepped down during ii) and iv) shown in the Figure:4.3.1, it does not affect
the operation.
Figure:4.3.1 Voltage Transition of VDD18 by Program
The setting example to change VDD18 from 1.1 V to 1.8 V at iii) in Figure:4.3.1 is shown below.
CPU outage in voltage transition: 32/f
SCLK
(f
SCLK
= 32.768 kHz, 977 µs)
..
Be sure to execute the setting in SLOW mode.
..
Step Setting Register name Description
1
Set CPU outage in voltage transition
PWCTR1
Set PWUPTM2-0 to "011".
2 Set output voltage, VDD18 PWCTR0 Set VDDLV1-0 to "10".
3 NOP instruction - Insert 3 NOP instructions.
4 Transition to NORMAL mode CPUM Set to "00000111".
1.1 V 1.3 V 1.1 V
VDD30
10 MHz
AX operating speed
Power ON
40 kHz 40 kHz
40 kHz
VDD30
VDD18 output voltage
VDD18 output
1.8 V
Operating mode
SLOW
NORMAL SLOW
i)
ii)
iii) iv)
1 MHz
1.8 V 1.1 V
SLOW NORMAL
1.3 V
1.1 V
00 01 00
VDDLV1-0
10
00
CPU idle time
CPU idle time