Chapter 4
Clock/ Mode/ Voltage Control
IV - 30 Voltage Control
Voltage Transition of VDD18 by Mode Transition
Figure:4.3.2 shows the example of voltage transition of VDD18 by mode transition. For the mode transition
method, refer to [4.2 Mode Control Function].
When the Deep STANDBY mode control, that change the voltage from 1.3 V or 1.8 V to 1.1 V, is enabled during
the mode transition from NORMAL to HALT2/STOP0, the STANBY mode with low-power consumption can be
set by just updating the CPUM register.
The Deep STANDBY mode is enabled by setting the PWCTR1.DEEPMOD to "1".
Figure:4.3.2 Voltage Transition of VDD18 by Mode Transition
The setting example of the transition to Deep STANDBY mode in Figure:4.3.2 is shown below.
Step Setting Register name Description
1
Set Deep STANDBY mode
PWCTR1
Set DEEPMOD to "1".
2 Set output voltage, VDD18 PWCTR0 Set VDDLV1-0 to "10".
3
Set the oscillation stabilization wait
and interrupt
DLYCTR
XXXICR
For the oscillation stabilization wait and inter-
rupt, refer to [2.5.3 Oscillation Stabilization Wait
Time] and [3.3 External Interrupts], respectively.
4 Transition to HALT2 mode CPUM Set to "00010101".
5 NOP instruction - Insert 3 NOP instructions.
1.8 V 1.1 V
VDD30
VDD30
VDD18 output voltage
VDD18 output
1.8 V
perating mode
NORMAL
NORMAL
1.8 V
HALT2 NORMAL
1.3 V
1.1 V
0 1
DEEPMOD
HALT2
CPU idle time
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