Panasonic MN101L Series

Chapter 3
Interrupts
III - 22 Control Registers
3.2.1 Non-maskable Interrupt (NMI) Control Register
 Non-maskable Interrupt (NMI) Control Register (NMICR: 0x03FE1)
When the undefined instruction is detected, IRQNPG is set to "1" and NMI occurs.
When the WDT overflows, IRQNWDG is set to "1" and NMI occurs.
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IRQNPG is not cleared by hardware. Before RTI instruction is executed in the NMI interrupt
handler, they must be cleared.
..
..
IRQNWDG is not cleared by hardware. Before RTI instruction is executed in the NMI inter-
rupt handler, they must be cleared.
..
bp 76543 2 1 0
Bit name-----IRQNPGIRQNWDGReserved
At reset000000 0 0
AccessRRRRRR/WR/WR/W
bp Bit name Description
7-3 - Always read as "0".
2 IRQNPG
Detection of Undefined instruction execution
0: Not detected
1: Detected
1 IRQNWDG
WDT overflow detection
0: Not detected
1: Detected
0 Reserved Must be set to "0".