Panasonic MN101L Series

Chapter 2
CPU
Extended Calculation Instruction II - 27
2.4.8 BCDSUBC BCD subtraction (with carry)
 Execution of BCD subtraction (with carry)
1. Store the 8-bit value of the two-digit BCD as a subtrahend to the D0 register. Store the 8-bit value of the two-
digit BCD as a minuend to the D1 register. Store the carry to the PSW.
2. Execute MOV 0x80, (0x03F07) (Extended calculation macro instruction BCDSUBC).
3. Subtracts the D0 register (8-bit) and the D1 register (8-bit) as the value of each two-digit BCD and subtracts
the PSW.CF further, and stores the result (8-bit) after the BCD correction to the D0 register.
..
When this extended calculation instruction is executed, the handy address (HA) is updated in
"0x03F07"
..
..
In this instruction, do not enter the value that can not be represented in BCD. If you enter it,
the result is not guaranteed.
..
BCDSUBC (MOV 0x80, (0x03F07)) VF NF CF ZF
00
zz
Operation
D0 (BCD) - D1 (BCD) - PSW.CF → D0 (BCD)
Subtracts the D0 register (8-bit) and the D1 register (8-bit) as the value of each two-
digit BCD and subtracts the PSW.CF further, and stores the result (8-bit) after the BCD
correction to the D0 register.
Bit Changes Size, Cycles, Codes
VF: 0
NF: 0
CF: Set if the result is smaller than "0", otherwise set to "0".
ZF: Set if the result is "0", otherwise set to "0".
6 nibbles
4 cycles
0000 0010 0111 0000 0000 1000