Chapter 14
DMA Controller
XIV - 12 DMA Data Transfer
14.3 DMA Data Transfer
There are two transfer modes, single transfer and burst transfer, which are selected with the DMCTR0H.DMTM.
14.3.1 Single Transfer Mode
When the DMA start trigger occurs, single data, the size of which is decided with DMCTR0H.DMUT, is trans-
ferred and the data transfer counter consisting of DMCNTH and DMCNTL are decremented by one. When all the
single data transfer finishes, DMA interrupt occurs.
If the DMA start trigger happens during the time after DMA reads the last single data from Source Address and
before the DMCTR1L.DMTEN is set to "1" by software (for example, the period (B) in the Figure:14.3.1), DMA-
AddReq interrupt occurs.
If the DMA start trigger happens during the time after the DMA start trigger occurs and before DMA reads the
data (not limited to the last single data) from Source Address (for example, the period (A) in the Figure:14.3.1),
DMA-Error interrupt occurs.
Figure:14.3.1 Example of Single Transfer
Read Write
DMA
start trigger
DMA
interrupt
DMCNTH
DMCNTL
3
DMA
Memory Access
Read Write
DMA
start trigger
Read Write
DMA
start trigger
Period (A)
2 1
DMTEN of
DMCTR1L
When DMA interrupt occurs,
the DMTEN is cleard to "0" by hardware.
0 N
Set the DMTEN to "1"
by software for next DMA.
Period (B)
Period (A)Period (A)
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