Panasonic MN101L Series

Chapter 5
Watchdog Timer (WDT)
WDT Control Register V - 3
5.2 WDT Control Register
5.2.1 WDT Control Register
 WDT Control Register (WDCTR: 0x03F02)
..
The WDCKSEL must be changed when the WDEN is "0". WDT starts operation by setting
the WDEN to "1", and the WDEN is not cleared except when the LSI is reset.
..
bp76543210
Bit name WDCKSEL - - - WDTS2-0 WDEN
At reset00000000
Access R/W R R R R/W R/W R/W R/W
bp Bit name Description
7 WDCKSEL
Select watchdog time clock source
0: SRCCLK
1: SOSCCLK
6-4 - Always read as 0.
3-1 WDTS2-0
Watchdog error detect period setup
000: 2
7
× (1/f
WDTCLK
)
001: 2
8
× (1/f
WDTCLK
)
010: 2
9
× (1/f
WDTCLK
)
011: 2
11
× (1/f
WDTCLK
)
100: 2
12
× (1/f
WDTCLK
)
101: 2
14
× (1/f
WDTCLK
)
110: 2
16
× (1/f
WDTCLK
)
111: 2
18
× (1/f
WDTCLK
)
0WDEN
WDT enable control
0: Disable
1: Enable