Chapter 3
Interrupts
III - 2 Overview
3.1 Overview
The LSI provides vectored interrupt services, consisting of LSI-reset, Non-Maskable Interrupts (NMI), and
Maskable Interrupts. The transition time from the interrupt occurrence to interrupt handler is 6 SYSCLK cycles at
a minimum, and the same amount of time is needed at a minimum when returning from the interrupt handler.
Each interrupt has a interrupt control register (hereinafter described as "xICR", and "x" is replaced with other
words. For example, in the case of Timer-0 interrupt control register, "x" is replaces with "TM0". All interrupt
control registers are described in [3.2 Control Registers].), which includes the interrupt request bit (IR), the inter-
rupt enable bit (IE) and the interrupt level bits (LV1-0).
IR is set to "1" by the corresponding interrupt trigger, and cleared to "0" when the interrupt is accepted.
IR can also be set and cleared by software.
IE controls the interrupt occurrence, and can be set and cleared only by software.
IE is valid when PSW.MIE is "1". NMICR (the interrupt control register of NMI) doesn’t have IE.
LV1-0 control the priority level of an interrupt. There is three levels of interrupt priority, and the lower vector
number has priority when several interrupts with the same interrupt priority level occur. A maskable interrupt is
accepted when LV1-0 is less than PSW.IM1-0. NMI is handled in priority to maskable interrupts.
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