Panasonic MN101L Series

Chapter 13
Serial Interface
XIII - 6 Overview
Figure:13.1.2 SCIFn (n = 2, 3) Block Diagram
IIC:Start condition generation IIC:Stop condition generation IIC:ACK/NACK added Clock Synchronous:last data set selection
SCnMD0.SCnCE1 SCnMD1.SCnSBTS
SCnMD1.SCnSBIS
HCLK/SCLK/SYSCLK
S E
L
SBOn
S E L
1/2
BRTM_S_EN.BRTM_Sn_EN
BRTM_S_MD.BRTM_Sn_MD
BRTM_S_CKSEL BRTM_S23_CK
SCnMD1.SCnIOM
BRTM_SCn_SCLK
SCnMD1.SCnMST
SBOnA SBOnB
S E
L
SC23SEL.SCnSEL1
SCnMD0.IIC3STE SCnMD3.IIC3STPC SCnMD3.IIC3ACKO SCnMD2.SCnFDC1-0
IIC:Arbitration lost detection(SCnIICSTR.IIC3ABT_LST) IIC:Slave address comparison(SCnIICSTR.IIC3ADD_ACC) IIC:Start condition detection(SCnIICSTR.IIC3STRT) IIC:General call detection(SCnIICSTR.IIC3GCALL) Clock Synchronous,IIC:Overrun error detection(SCnSTR.SCnORE)
SCnMD1.SCnSBOS
SBOn
SBIn
SBInA SBInB
S E
L
SC23SEL.SCnSEL0
SBTn
SBTnA
SBTnB
S E
L
SC23SEL.SCnSEL2
S E
L
SBOnA SBOnB
S E L
SC23SEL.SCnSEL1
SBTn
SBTnA SBTnB
S E L
SC23SEL.SCnSEL3
SCnMD1.SCnMST
SCnMD2.SCnSBCSEN SCnMD2.SCnSBCSLV
Reception shift register
Transmission control circuit
Transmit shift register
Transmission buffer
SCnMD0.SCnDIR
Read/Write
SCnRDB
SCnTRB
RXBUFn TXBUFn
SWAP MSB<->LSB
Clock I/O pin
BRTM
Counter
Compare register
BRTM_Sn_OC
Reception buffer
Comparator
Prescaler
(BRTM output clock)
Baud rate timer (BRTM)
Reception control circuit
I/O control
Polar control
Data input pin
Data output pin
I/O control
Chip select I/O pin
Chip select
generation circuit
I/O control
Polar control