Panasonic MN101L Series

Chapter 20
Appendix
XX - 6 Instruction set
Mnemonic
*1
*2
*10
*10
*3
*6
*1
*6
*7
*6
*7
*8
*1
*4
*5
*1
*2
*9
1
1101
0000
0000
1000
0100
1100
0000
1111
0001
1110
0000
1001
0011
1000
0000
1011
0101
0101
1110
1110
0101
1111
1111
1111
0101
1000
1001
1010
1000
1010
1011
0100
0100
0100
0100
1111
1110
0010
1100
0000
0000
1101
1000
0101
0000
1100
1101
0111
0001
1001
0110
0001
1001
1010
1010
2
111a
100a
101A
00Dd
11Da
11Ad
00Aa
10Dn
011A
10Dn
011A
000d
DnDm
00Dm
10Dm
DnDm
00Dd
10Da
110a
110a
011a
1101
1100
1100
010d
1aDn
1aDn
DnDm
01Dn
DmDm
DnDm
00Dd
10Da
010d
011a
111D
111d
DnDm
00Dm
0100
0101
1000
01Dd
11Da
01Aa
110d
110a
DnDm
11Dm
0010
DnDm
10Dm
0011
DnDm
DmDm
3
<#16
<#4>
<#8.
<#4>
<#8.
<#16
<#4>
<#8.
<#16
<#16
<#8.
<#16
<#16
<#8.
<abs
<abs
<abs
<#16
<#16
<#8.
<#8.
<#8.
<#8.
<#8.
4
....
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8..>
12..
16..
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...>
...>
...>
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...>
5
....
....
....
....
....
....
<#8.
...>
....
....
....
6
...>
...>
...>
...>
...>
...>
...>
<#8.
...>
...>
...>
7
...>
<#8.
8
...>
91011Ext.
0010
0010
0010
0010
0010
0010
0011
0011
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0010
0010
0010
0011
0010
0011
0010
0011
0011
{
{
{
{
{
{
{
{
6
3
3
3
3
3
3
2
2
2
2
3
3
3
4
3
3
3
3
5
7
3
4
7
7
3
3
3
2
5
3
3
3
7
7
3
3
3
4
6
7
9
3
3
3
6
6
3
4
5
3
4
5
3
5
1
1
1
1
1
1
1
1+d
1+d
1+d
1+d
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
9
1
1
3+d
3+d
3+d
1
1
1
1
1
1
1
2
1
1
2
1
1
imm16 → Am
SP → Am
An → SP
DWn → DWm
DWn → Am
An → DWm
An → Am
SP - 1 → SP, Dn → mem8(SP)
SP - 2 → SP, An → mem16(SP)
mem8(SP) → Dn, SP + 1 → SP
mem16(SP) → Dn, SP + 2 → SP
sign(Dn) → DWm
Dm + Dn → Dm
Dm + sign(imm4) → Dm
Dm + imm8 → Dm
Dm + Dn + CF → Dm
DWm + DWn → DWm
Am + DWn → Am
Am + sign(imm4) → Am
Am + sign(imm8) → Am
Am + imm16 → Am
SP + sign(imm4) → SP
SP + sign(imm8) → SP
SP + imm16 → SP
DWm + imm16 → DWm
Am + zero(Dn) → Am
Am + sign(Dn) → Am
Dm - Dn → Dm
Dn - Dn → Dn
Dm - imm8 → Dm
Dm - Dn - CF → Dm
DWm - DWn → DWm
Am - DWn → Am
DWm - imm16 → DWm
Am - imm16 → Am
Dm * Dn → DWk
DWm / Dn → DWm-l ⋅⋅⋅ DWm-h
Dm - Dn ... PSW
Dm - imm8 ... PSW
mem8(abs8) - imm8 ... PSW
mem8(abs12) - imm8 ... PSW
mem8(abs16) - imm8 ... PSW
DWm - DWn ... PSW
Am - DWn ... PSW
Am - An ... PSW
DWm - imm16 ... PSW
Am - imm16 ... PSW
Dm & Dn → Dm
Dm & imm8 → Dm
PSW & imm8 → PSW
Dm | Dn → Dm
Dm | imm8 → Dm
PSW | imm8 → PSW
Dm ^ Dn → Dm
Dm ^ imm8 → Dm
MOVW imm16, Am
MOVW SP, Am
MOVW An, SP
MOVW DWn, DWm
MOVW DWn, Am
MOVW An, DWm
MOVW An, Am
PUSH Dn
PUSH An
POP Dn
POP An
EXT Dn, DWm
ADD Dn, Dm
ADD imm4, Dm
ADD imm8, Dm
ADDC Dn, Dm
ADDW DWn, DWm
ADDW DWn, Am
ADDW imm4, Am
ADDW imm8, Am
ADDW imm16, Am
ADDW imm4, SP
ADDW imm8, SP
ADDW imm16, SP
ADDW imm16, DWm
ADDUW Dn, Am
ADDSW Dn, Am
SUB Dn, Dm ( Dn ≠ Dm )
SUB Dn, Dn
SUB imm8, Dm
SUBC Dn, Dm
SUBW DWn, DWm
SUBW DWn, Am
SUBW imm16, DWm
SUBW imm16, Am
MULU Dn, Dm
DIVU Dn, DWm
CMP Dn, Dm
CMP imm8, Dm
CMP imm8, (abs8)
CMP imm8, (abs12)
CMP imm8, (abs16)
CMPW DWn, DWm
CMPW DWn, Am
CMPW An, Am
CMPW imm16, DWm
CMPW imm16, Am
AND Dn, Dm
AND imm8, Dm
AND imm8, PSW
OR Dn, Dm
OR imm8, Dm
OR imm8, PSW
XOR Dn, Dm
XOR imm8, Dm
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1
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z
PUSH
POP
EXT
ADD
ADDC
ADDW
ADDUW
ADDSW
SUB
SUBC
SUBW
MULU
DIVU
CMP
CMPW
AND
OR
XOR
Group NotesREPOperation
VF NF CF ZF
Code
Size
Execution
Cycle
Machine Code
MN101L SERIES INSTRUCTION SET
Flag
*1 D = DWn, d = DWm
*2 A = An, a = Am
*3 d = DWm
*4 D = DWk
*5 D = DWm
*6 #4 sign-extention
*7 #8 sign-extention
*8 Dn zero-extention
*9 m ≠ n
*10 When the access address is odd number, the execution cycle is added "( 1 + d )"
Arithmetic Instructions
Bitwise Logical Instructions