Panasonic MN101L Series

Chapter 20
Appendix
Instruction set XX - 7
Mnemonic
*1 *4
*2 *4
*3 *4
*1 *4
*2 *4
*3 *4
*2 *4
*3 *4
*2 *4
*3 *4
*2 *4
*3 *4
*2 *4
*3 *4
*2 *4
*3 *4
*2 *4
*3 *4
1
0010
0011
0011
0010
1000
1011
1100
1000
1011
1100
0000
1101
1001
1000
1001
1001
1000
1001
1000
1001
1000
1001
1000
1001
1000
1001
1000
1001
0010
0011
2
10Dn
10Dn
11Dn
11Dn
0bp.
0bp.
0bp.
1bp.
1bp.
1bp.
11Dm
0bp.
000H
1010
1010
001H
1011
1011
1000
1000
1100
1100
1101
1101
1110
1110
1111
1111
0001
0001
3
<io8
<abs
<abs
<io8
<abs
<abs
<#8.
<abs
<d4>
<d7.
<d11
<d4>
<d7.
<d11
<d7.
<d11
<d7.
<d11
<d7.
<d11
<d7.
<d11
<d7.
<d11
<d7.
<d11
4
...>
8..>
16..
...>
8..>
16..
...>
16..
...H
....
...H
....
...H
....
...H
....
...H
....
...H
....
...H
....
...H
....
5
....
....
....
...H
...H
...H
...H
...H
...H
...H
...H
6
...>
...>
...>
7
8 9 10 11Ext.
0010
0010
0010
0010
0011
0011
0011
0011
0010
0011
0010
0010
{
{
{
3
3
3
3
5
4
7
5
4
7
5
7
3
4
5
3
4
5
4
5
4
5
4
5
4
5
4
5
5
6
1
1
1
1
2+2d
2+2d
2+2d
2+2d
2+2d
2+2d
1
2+d
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
1/3+i
~Dn → Dm
Dn.msb → temp, Dn.lsb → CF
Dn >> 1 → Dn, temp → Dn.msb
Dn.lsb → CF, Dn >> 1 → Dn
0 → Dn.msb
Dn.lsb → temp, Dn >> 1 → Dn
CF → Dn.msb, temp → CF
mem8(IOTOP+io8) & bpdata...PSW
1 → mem8(IOTOP+io8)bp
mem8(abs8) & bpdata...PSW
1 → mem8(abs8)bp
mem8(abs16) & bpdata...PSW
1 → mem8(abs16)bp
mem8(IOTOP+io8) & bpdata...PSW
0 → mem8(IOTOP+io8)bp
mem8(abs8) & bpdata...PSW
0 → mem8(abs8)bp
mem8(abs16) & bpdata...PSW
0 → mem8(abs16)bp
Dm & imm8...PSW
mem8(abs16) & bpdata...PSW
if(ZF=1), PC+3+d4(label)+H → PC
if(ZF=0), PC+3 → PC
if(ZF=1), PC+4+d7(label)+H → PC
if(ZF=0), PC+4 → PC
if(ZF=1), PC+5+d11(label)+H → PC
if(ZF=0), PC+5 → PC
if(ZF=0), PC+3+d4(label)+H → PC
if(ZF=1), PC+3 → PC
if(ZF=0), PC+4+d7(label)+H → PC
if(ZF=1), PC+4 → PC
if(ZF=0), PC+5+d11(label)+H → PC
if(ZF=1), PC+5 → PC
if((VF^NF)=0), PC+4+d7(label)+H → PC
if((VF^NF)=1), PC+4 → PC
if((VF^NF)=0), PC+5+d11(label)+H → PC
if((VF^NF)=1), PC+5 → PC
if(CF=0), PC+4+d7(label)+H → PC
if(CF=1), PC+4 → PC
if(CF=0), PC+5+d11(label)+H → PC
if(CF=1), PC+5 → PC
if(CF=1), PC+4+d7(label)+H → PC
if(CF=0), PC+4 → PC
if(CF=1), PC+5+d11(label)+H → PC
if(CF=0), PC+5 → PC
if((VF^NF)=1), PC+4+d7(label)+H → PC
if((VF^NF)=0), PC+4 → PC
if((VF^NF)=1), PC+5+d11(label)+H → PC
if((VF^NF)=0), PC+5 → PC
if((VF^NF) | ZF=1),
PC+4+d7(label)+H → PC
if((VF^NF) | ZF=0),
PC+4 → PC
if((VF^NF) | ZF=1),
PC+5+d11(label)+H → PC
if((VF^NF) | ZF=0),
PC+5 → PC
if((VF^NF) | ZF=0),
PC+4+d7(label)+H → PC
if((VF^NF) | ZF=1),
PC+4 → PC
if((VF^NF) | ZF=0),
PC+5+d11(label)+H → PC
if((VF^NF) | ZF=1),
PC+5 → PC
NOT Dn
ASR Dn
LSR Dn
ROR Dn
BSET (io8)bp
BSET (abs8)bp
BSET (abs16)bp
BCLR (io8)bp
BCLR (abs8)bp
BCLR (abs16)bp
BTST imm8, Dm
BTST (abs8)bp
BEQ label
BEQ label
BEQ label
BNE label
BNE label
BNE label
BGE label
BGE label
BCC label
BCC label
BCS label
BCS label
BLT label
BLT label
BLE label
BLE label
BGT label
BGT label
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
z
z
0
z
z
z
z
z
z
z
z
z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
z
z
z
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
z
z
z
z
z
z
z
z
z
z
z
z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NOT
ASR
LSR
ROR
BSET
BCLR
BTST
Bcc
Group REP NotesOperation
VF NF CF ZF
Code
Size
Execution
Cycle
Machine Code
MN101L SERIES INSTRUCTION SET
Flag
*1 d4 sign-extention
*2 d7 sign-extention
*3 d11 sign-extention
*4 not taken / taken
Bit manipulation Instructions
Branch Instructions