Panasonic MN101L Series

Chapter 3
Interrupts
Overview III - 11
 Maskable Interrupt Processing
The following figure shows the processing sequence when the lower priority level interrupt occurs while process-
ing the higher priority level interrupt.
(Interrupt 1: LV1-0 = "00", Interrupt 2: LV1-0 = "10", Interrupt 3: LV1-0 = "11")
Figure:3.1.6 Processing Sequence for Maskable Interrupts
Main program
PSW.MIE="1"
PSW.IM1-0="11"
Interrupt handler: 1
RTI
Interrupt 1 occurs
(LV1-0="00")
IM1-0="00"
When MIESET is "0", MIE is set to "0"
When MIESET is "1", MIE is set to "1"
Interrupt 2 occurs
(LV1-0="10")
*1
)
(
Interrupt 3 generated
(LV1-0="11")
IM1-0="11"
)(
RTI
Interrupt handler: 2
IM1-0="11"
)(
*2
MIE="0"
IM1-0="00"
)
(
Reset
Accepted because LV1-0 < IM1-0 and MIE = "1"
Not accepted because LV1-0 = IM1-0
Interrupt acceptance cycle
Interrupt acceptance cycle
Interrupt 2 is not accepted because LV1-0 ("10") > PSW.IM1-0 ("00").*1 :
After the RTI execution of Interrupt 1, Interrupt 2 is accepted because LV1-0 ("10")
< PSW.IM1-0 ("11"
).
*2 :
Parentheses () indicates hardware processing.
)
(
IM1-0="10"
When MIESET is "0", MIE is set to "0"
When MIESET is "1", MIE is set to "1"