Chapter 3
Interrupts
III - 16 Overview
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xICR.IR is set when the corresponding interrupt occurs or the edge switching of the interrupt
is done, regardless of the value of xICR.IE. Clear IR to "0" following the setup procedures (4)
to (6).
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Before operating xICR, set PSW.MIE to "0". There's no guarantee of proper operation when
writing to xICR while PSW.MIE is "1".
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Always set MEMCTR.IRWE to "0" except when writing xICR.IR by software.
The interrupt request may be cleared when operating xICR by software while the MEM-
CTR.IRWE is "1". For example, when the bit operation to xICR is executed (xICR is read,
modified, and overwritten by CPU), the interrupt request, which occurs during the above
read-to-write cycle is cleared because IR is overwritten with "0" by software. To avoid this,
set MEMCTR.IRWE to "0", which prevent the interrupt missing by software.
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Before setting MEMCTR.MIESET, set PSW.MIE to "0". There's no guarantee of proper oper-
ation when writing to MEMCTR.MIESET while PSW.MIE is "1".
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