Chapter 4
Clock/ Mode/ Voltage Control
IV - 4 Clock Control
CPU Mode Control Register (CPUM: 0x03F00)
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Set the CPUM in one of states described in Table 4.1.2.
(Any other value which is not described in the Table 4.1.2. must not be set to the CPUM.)
The LSI has the following function to prevent malfunction.
HALT = 0, CLKSEL = 1 and OSCMOD = 0 is not be valid.
CLKSEL = 0 and XIMOD = 0 is not valid.
STOP = 1 and HALT = 1 is not valid.
OCDMOD = 0 and XIMOD = 0 is not valid.
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Set the PSW.MIE to "0" before changing the data of CPU or CKCTR.
Insert 3 NOP instructions right after the instruction for changing CPUM or CKCTR.
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The instruction for changing the data of CPUM or CKCTR must not be executed in the inter-
nal RAM.
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bp76543210
Bit name - - STOP HALT HALTMOD XIMOD OSCMOD CLKSEL
Initial value 0 0 0 0 0 1 0 0
Access R R R/W R/W R/W R/W R/W R/W
bp Bit name Description
7-6 - Always read as "00".
5STOP
STOP mode request
0: not STOP mode
1: STOP mode
4HALT
HALT mode request
0: not HALT mode
1: HALT mode
3HALTMOD
HALT1/HALT3 mode control
0: Go to HALT1 mode
1: Go to HALT3 mode
2XIMOD
Low-speed oscillation control
0: Low-speed oscillation disabled
1: Low-speed oscillation enabled
1OSCMOD
High-speed oscillation control
0: High-speed oscillation disabled
1: High-speed oscillation enabled
0 CLKSEL
Select clock control
0: Low-speed clock (SCLK)
1: High-speed clock (HCLK)
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