Chapter 6
Power Supply Voltage Detection
VI - 8 Setting Example
..
An interrupt may be generated between the step (9) and step (10).
In that case, after returning from the interrupt, CPU enters STOP mode although V
DD30
is
higher than V
LVI
. It prevents returning from STOP mode at rising of the power supply voltage.
To avoid such operation, refer to the addresses saved to stack in interrupt processing. If it is
considered that the operation as above occurred, rewrite the value of stack address or saved
data to prevent the standby transition program execution.
..
(10) When the LVIOUT bit is "0", operating
mode transits to STOP mode
CPUM (0x03F00)
bp3: STOP = 1
(10) When the monitored LVIOUT bit is "0", the operating
mode transits to STOP mode.
(11) Return from STOP mode by interrupt (11) When the power supply voltage exceeds 2.0 V, an
interrupt is generated to return from STOP mode.
Setup Procedure Description
To Next Page
Loading...
