Chapter 7
I/O Port
VII - 50 Port 5
Table:7.9.4 P52 Function Selection
*1 When serial data is output, set the P5DIR.P5DIR2 to "1".
*2 When serial data is input and output, set the bit to "1".
Table:7.9.5 P53 Function Selection
*1 When the LSI is the master of Clock-synchronous communication, set the P5DIR.P5DIR3 to "1".
Table:7.9.6 P54 Function Selection
*1 When the LSI outputs the chip select signal, set the P5DIR.P5DIR4 to "1".
Table:7.9.7 P55 Function Selection
Setup Function
Register LCCTR2 SC3MD1 SC23SEL
Bit name SEGSL17 SC3SBOS SC3SBIS SC3IOM SC3SEL1
1----SEG17
0
1 (*1) - (*2) - (*2) 1
SBO3B/
SDA3B
0
111
00-P52
Setup Function
Register LCCTR2 SC3MD1 SC23SEL
Bit name SEGSL16 SC3SBTS SC3SEL2
1 - - SEG16
0
1 (*1) 1 SBT3B/SCL3B
0- P53
Setup Function
Register LCCTR2 KEYIEN KEYSEL SC3MD2 SC23SEL
Bit name
SEGSL15 KEYI0EN KEY0SEL
SC3SBCS
EN
SC3SEL3
1 - - - - SEG15
0
1 1 0 - KEY0B
0-
1 (*1) 1 SBCS3B
0-P54
Setup Function
Register LCCTR2 KEYIEN KEYSEL TMIOEN0 TM1MD TMIOSEL0
Bit name SEGSL14 KEYI1EN KEY1SEL TM1OEN TM1CK1-0 TM1IOSEL
1 - - - - - SEG14
0
1 1 0 Other than 11 - KEY1B
0-
1 Other than 11 0 TM1IO (output)
0
11 0 TM1IO (input)
Other than 11 - P55
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