Panasonic MN101L Series

Chapter 1
Overview
Hardware Features I - 5
* MN101LR03D
Serial Interface 3: Clock synchronous serial cannot be used 3 and 4-wire communication,
and is not compatible with SPI. (Chip select pin is not assigned.)
* MN101LR02D
Serial Interface 1: Not implemented
Serial Interface 3: Clock synchronous serial cannot be used 4-wire communication,
and is not compatible with SPI. (Chip select pin is not assigned.)
• A/D Converter (ADC): 1 unit
- Resolution : 12 bits
- Analog signal input channel: 8 channels
* MN101LR04D : 6 channels
* MN101LR03D : 4 channels
* MN101LR02D : 3 channels
• I/O ports: 69 pins
- Selectable N-channel transistor drive strength: 55 pins
* MN101LR04D: 53 pins (selectable N-channel transistor drive strength: 41 pins)
* MN101LR03D: 37 pins (selectable N-channel transistor drive strength: 27 pins)
* MN101LR02D: 22 pins (selectable N-channel transistor drive strength: 19 pins)
• Clock Output
- HCLK, SCLK, SYSCLK or RTCCLK can be output.
• Automatic Reset Circuit
• Low-voltage Detection Circuit (LVI)
•LCD Driver
- 43 segment outputs, 4 common outputs (39 segment outputs, 8 common outputs)
- Display mode: Static, 1/2 to 1/8 duty
- Bias : 1/2, 1/3 (Built-in boost/ External resistor divider)
* MN101LR04D
31 segment outputs
4 common outputs
Display mode: Static, 1/2 to 1/4 duty
* MN101LR03D
21 segment outputs
4 common outputs
Display mode: Static, 1/2 to 1/4 duty
* MN101LR02D does not have LCD driver function.