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Panasonic MN101L Series

Panasonic MN101L Series
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Chapter 8
8-bit Timer
VIII - 32 8-bit Timer Cascade Connection
The binary counters and the compare registers corresponding to two timers in cascade connection operate as a 16-
bit register, respectively. When activating the timer, set the TMnMD.TMnEN for lower 8-bit timer to "1".
A waveform of the timer pulse and an interrupt request is output from the upper 8-bit timer.
Select the clock source with the register for the lower 8-bit timer.
Other settings and the timing to count are the same as a single 8-bit timer operation.
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When using Timer 0 connected with Timer 1 in cascade, a timer pulse and an interrupt
request are output from Timer 1. "Low" fixed data are output from Timer 0 as the timer pulse.
Timer 0 interrupt should be disabled though any interrupt request of Timer 0 is not generated.
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When using Timer 2 connected with Timer 3 in cascade, a timer pulse and an interrupt
request are output from Timer 3. "Low" fixed data are output from Timer 2 as the timer pulse.
Timer 2 interrupt should be disabled though any interrupt request of Timer 2 is not generated.
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When using Timer 4 connected with Timer 5 in cascade, a timer pulse and an interrupt
request are output from Timer 5. "Low" fixed data are output from Timer 4 as the timer pulse.
Timer 4 interrupt should be disabled though any interrupt request of Timer 4 is not generated.
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At 16-bit cascade connection, when rewriting the compare register to clear the binary
counter, set the TMnMD.TMnEN for lower 8-bit timer to "0" to stop counting. Then rewrite the
compare registers.
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Use a 16-bit access instruction to set (TM1OC to TM0OC) register, (TM2OC to TM3OC)
register and (TM5OC to TM4OC) register.
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During cascade connection, PWM output function cannot be used. When cascade connec-
tion, always set the TMnMD.TMnPWM to "0".
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When cascade connection, read the value of TMnBC with the 16-bit access instruction,
MOVW.
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