Panasonic MN101L Series

Chapter 9
16-bit Timer
Overview IX - 3
 16-bit Timer n Block Diagram (n = 7, 8 and 9)
Figure:9.1.1 16-bit Timer n Block Diagram (n = 7, 8 and 9)
16bit Preset Register1
(TMnPR1H, TMnPR1L)
16bit Capture Register
(TMnICH, TMnICL)
16bit Compaer Register1
(TMnOC1H, TMnOC1L)
16bit Bynary Counter
(TMnBCH, TMnBCL)
Match detection
Match detection
TMnOC2IRQ
M
U
X
overflow
M
U
X
M
U
X
TMnIRQ
16bit Compare Register2
(TMnOC2H, TMnOC2L)
16bit Preset Register2
(TMnPR2H, TMnPR2L)
8bit Dead time Counter(*1)
Timer/PWM output generation
IGBT output generation(*1)
TMnIO
HCLK
HCLK/2
HCLK/4
HCLK/16
SCLK
SCLK/2
SCLK/4
SCLK/16
SYSCLK
SYSCLK/2
SYSCLK/4
SYSCLK/16
TMnIO input
TMnIO input/2
TMnIO input/4
TMnIO input/16
Match detection
*1 Function of Timer 7 only
8bit Dead time Preset Register1(*1)
(TM7DPR1)
8bit Dead time Preset Register2(*1)
(TM7DPR2)
8bit Dead time Compare Register(*1)