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Panasonic MN101L Series

Panasonic MN101L Series
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Chapter 9
16-bit Timer
16-bit Timer Control Registers IX - 17
Timer 8 Mode Register 4 (TM8MD4: 0x03F9F)
..
The TM8MD4.T8CAPCLR is valid when the timer is in active. Note that the binary counter is
not cleared when capturing data while the timer is stopped.
..
..
Set the Timer 8 mode registers while the TM8MD1.TM8EN is "0". And the TM8MD1.TM8EN
must not be changed at the same time as the other bit.
..
bp765432 1 0
Bit name------T8ICT2T8CAPCLR
At reset000000 0 0
AccessRRRRRRR/WR/W
bp Bit name Description
7-2 - Always read as 0.
1T8ICT2
Select capture trigger
0: Timer 0 interrupt
1: Timer 1 interrupt
0T8CAPCLR
Binary counter clear enable at capture
0: Disabled (not cleared)
1: Enabled (cleared)

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