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Panasonic MN101L Series

Panasonic MN101L Series
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Chapter 9
16-bit Timer
16-bit High-Precision PWM Output (with Continuously Variable Period/Duty) IX - 37
Count Timing of High-Precision PWM Output
(when compare register 2 is set to "compare register 1" - 1)
Figure:9.7.3 Count Timing of High-Precision PWM Output (When TMnOC2 is set to TMnOC1 - 1)
..
When outputting the high-precision PWM, set the TMnMD2.TMnBCR to "1" to select
TMnOC1 compare match as the binary counter clear source and the PWM set source (to
"High" state).
Also, set the TMnMD2.TnPWMSL to "1" to select TMnOC2 compare match as the PWM
reset source (to "Low" state).
..
..
The PWM output at the initial state is "Low". It changes to "High" at the time the PWM opera-
tion is selected by setting the TMnMD2.TMnPWM.
..
..
When outputting the high-precision PWM, set the values of TMnOC1 and 2 as follow:
TMnOC2 < TMnOC1
If TMnOC2 TMnOC1, the PWM output is fixed to "High".
..
Count
clock
TMnEN
bit
Compare
register 2
Binary
counter
TMnIO output
(PWM output)
Compare
register 1
N
N-1
N-1
N
0000 00010000 0001

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