Panasonic MN101L Series

Chapter 9
16-bit Timer
IX - 40 16-bit Timer Capture Function
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When the system clock (SYSCLK) is selected as the capture clock by setting the
TMnMD3.TMnCKSMP to "1", the clock for the binary counter is the one that is selected by
setting the TMnMD1.TMnCK1-0 and synchronized with SYSCLK.
However, if HCLK or SYSCLK is selected with the TMnMD1.TMnCK1-0, the binary counter
doesn't count correctly. When selecting HCLK or SYSCLK, set the TMnMD3.TMnCKSMP to
"0".
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Each capture trigger signal of the 16-bit timers, Timer 7-9 is generated by sampling at the ris-
ing edge of the capture clock selected with the TMnMD3.TMnCKSMP.
Therefore, even if a capture trigger is input, the value of the binary counter is not loaded to
the capture register until at the 2nd rising edge of the capture clock from the capture trigger.
If the clock which is slower than the CPU operation speed (f
SYSCLK
) is used as the timer
source clock, set the TMnMD3.TMnCKSMP to "SYSCLK".
Also, the interval of each capture trigger should be set more than twice the clock cycle which
is set in the TMnMD3.TMnCKSMP.
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If the capture clock cycle is longer than the system clock, the value of the capture register
may be read out before capturing.
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