Panasonic MN101L Series

Chapter 13
Serial Interface
XIII - 30 Clock-Synchronous Communication
 Setting of Transfer Clock (SCnCLK)
SCIFn (n = 0, 1) operates with SCnCLK which is generated based on BRTM output clock (BRTM_SCnCLK).
When SCnMD1.SCnCKM is "0", SCnCLK is the same as BRTM_SCnCLK.
When SCnMD1.SCnCKM is "1", SCnCLK is as follows:
When SCnMD1.SCnDIV is "0", SCnCLK is BRTM_SCnCLK divided by 8.
When SCnMD1.SCnDIV is "1", SCnCLK is BRTM_SCnCLK divided by 16.
SCnCLK of SCIF (n = 2, 3) is the same as BRTM_SCnCLK.
When the LSI is a master, SCnCLK is output from SBTn as a transfer clock.
When the LSI is a slave, set the frequency of SCnCLK to the value faster than the transfer clock’s and as close to
the transfer clock’s as possible.
 Generating Baud Rate Timer Output Clock (BRTM_SCnCLK)
SCIFn has a dedicated Baud Rate Timer (BRTMn).
Select a count clock for BRTMn with BRTM_S_CKSEL, BRTM_S01_CK, and BRTM_S23_CK.
When BRTM_S_EN.BRTM_Sn_EN is set to "1", the binary counter of BRTMn (BRTM_Sn_BC) starts counting
up. When BRTM_Sn_BC becomes equal to BRTM_Sn_OC, BRTM_Sn_BC is cleared at the next count clock
and restarts counting up.
While the duty of BRTM_SCnCLK is "1:1" (BRTM_S_MD.BRTM_Sn_MD is "0"), the cycle and operation of
BRTMn are shown in the figure below.
BRTM_SnCLK Cycle = 2 × (N + 1) × Count Clock Cycle (N: Setting value of BRTM_Sn_OC)
Figure:13.3.1 BRTMn Count Operation (Duty: 1:1, Count Clock: HCLK, N: 0x00)
Figure:13.3.2 BRTMn Count Operation (Duty: 1:1, Count Clock: HCLK, N: 0x01)
8'h00
HCLK
SYSCLK
BRTM_Sn_EN
BRTN_Sn_BC
BRTM_SnCLK
8'h00
8'h01 8'h00 8'h01 8'h00
8'h01
8'h00 8'h01
8'h00
8'h01
8'h00
8'h01
HCLK
SYSCLK
BRTM_Sn_EN
BRTN_Sn_BC
BRTM_SnCLK