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Panasonic MN101L Series

Panasonic MN101L Series
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Chapter 13
Serial Interface
Clock-Synchronous Communication XIII - 43
Data Transmission/Reception (1-byte Communication Mode)
Data Transmission (1-byte Communication Mode)
Step Setting Register name Description
1
Empty confirmation of transmis-
sion buffer
SCnSTR.SCnTEMP Confirm that SCnSTR1.SCnTEMP is 0.
2 Data write to TXBUFn TXBUFn Set transmission data in TXBUFn.
3
Wait for communication comple-
tion
<SCIFn (n = 0, 1)>
SCnSTR.SCnTBSY
SCnSTR.SCnRBSY
<SCIFn (n = 2, 3)>
SCnSTR.SCnTBSY
<SCIFn (n = 0, 1)>
When the communication has been completed, SCnTBSY and
SCnRBSY become 0.
When an interrupt is enabled, a communication complete inter-
rupt (SCnTIRQ) occurs.
<SCIFn (n = 2, 3)>
When the communication has been completed, SCnTBSY
becomes 0.
When an interrupt is enabled, a communication complete inter-
rupt (SCnTIRQ) occurs.
4
Reception data read from
RXBUFn.
RXBUFn Read out the reception data from RXBUFn.
5
Confirmation of overrun error <SCIFn (n = 0, 1)>
SCnSTR.SCnORE
SCnSTR.SCnERE
<SCIFn (n = 2, 3)>
SCnSTR.SCnORE
If SCnORE/SCnERE(*) is 1, it indicates an overrun error has
occurred. When an overrun error has occurred, take mea-
sures, such as data retransmission, since reception data may
be destroyed.
(*) SCnERE is only for SCIFn (n = 0, 1).
6
Transmission/reception end - Repeat these procedures from step 1 to execute the next com-
munication.
Step Setting Register name Description
1
Empty confirmation of transmis-
sion buffer
SCnSTR.SCnTEMP Confirm that SCnSTR1.SCnTEMP is 0.
2 Data write to TXBUFn TXBUFn Set transmission data in TXBUFn.
3
Wait for communication comple-
tion
<SCIFn (n = 0, 1, 2, 3)>
SCnSTR.SCnTBSY
<SCIFn (n = 0, 1, 2, 3)>
When the communication has been completed, SCnTBSY
becomes 0.
When an interrupt is enabled, a communication complete inter-
rupt (SCnTIRQ) occurs.
4
Transmission end - Repeat these procedures from step 1 to execute the next com-
munication.

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