Chapter 13
Serial Interface
XIII - 60 IIC Communication
Clock Extension in Master Communication
SCLn is sampled at falling edges of SCnCLK in Standard Mode, or rising edges of SCnCLK in High-speed
Mode. When the transfer clock output from the LSI is "High" but SCLn is "Low", the high period of the transfer
clock is extended since the slave device keeps SCLn "Low".
Figure:13.5.3 SCLn without "Low" Period Extension by Slave Device (Standard Mode)
Figure:13.5.4 SCLn with "Low" Period Extension by Slave Device (Standard Mode)
Transfer rate = SCnCLK divided by 8
3.5 ×(SCnCLK)
SCLn
SCnCLK
SDAn
Transfer clock
output from the LSI
Transfer rate = SCnCLK divided by 9
"High" period extension
"Low" period extension by slave
3.5 ×(SCnCLK)
SCLn
SCnCLK
SDAn
Transfer clock
output from the LSI
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