Panasonic MN101L Series

Chapter 16
A/D Converter (ADC)
XVI - 14 Operation
 Sample Hold Time
This LSI contains a sample hold capacitor (C
AD
= 16 pF), input pin capacitor (C
IO
= 2 pF) and resistor (R
AD
= 4.0
kΩ).
Set the sample hold time (T
AD
) based on the time constant (τ) with C
AD
, C
IO
, R
AD
and impedance (R
OUT
) of
external analog signal output circuit.
It is recommended to select to be T
AD
> 8τ (τ = RC).
For example, when R
OUT
= 10 kΩ, T
AD
is determined as follows.
R = 10 kΩ + 4.0 kΩ = 14 kΩ
C = 2 pF + 16 pF = 18 pF * R and C will be simplified to calculate.
8RC = 2.0 µs
Set the conversion clock that T
AD
> 2.0 µs
When the setting of sample hold time (ANCTR0.ANSH1-0) is "T
ADCLK
× 2", set A/D conversion
clock (ADCLK) < 1.0 MHz.
Figure:16.3.5 Circuit Example
 External Capacitor
When R
OUT
is large, the input load will essentially comprise only R
AD
, C
AD
and C
IO
by providing a large-capac-
itance (1000 pF to 1 µF) outside.
It is also recommended that a large-capacitance is added to outside as the protection against noise for the analog
signal.
In this case, ADC may not be possible to follow the analog signal with the large differential coefficient by an
external capacitor affecting as a low-path filter.
When converting a high-speed analog signal, insert a low-impedance buffer.
* When using this ADC, evaluate enough that A/D conversion is ensured the expected precision.
Figure:16.3.6 Circuit Example with External Capacitor
External analog signal
outut circuit
LSI
R
OUT
CIO
RAD
2 pF
4.0 kΩ
C
AD
16 pF
Equivalent circuit of ADC
External analog signal
outut circuit
LSI
R
OUT
CIO
RAD
2 pF
1000 pF
to 1 µF
4.0 kΩ
C
AD
16 pF
Equivalent circuit of ADC