Panasonic MN101L Series

Chapter 17
LCD
XVII - 8 Control Registers
 LCD Mode Control Register 3 (LCDMD3: 0x03E83)
 LCD Mode Control Register 4 (LCDMD4: 0x03ECE)
bp 76543210
Bit name Reserved LCCK3-0 LCCKS2-0
At reset00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
bp Bit name Description
7 Reserved Must be set to "0".
6-3 LCCK3-0
LCDCLK selection
0000: LCDCLKS/2
3
0001: LCDCLKS/2
4
0010: LCDCLKS/2
5
0011: LCDCLKS/2
6
0100: LCDCLKS/2
7
0101: LCDCLKS/2
8
0110: LCDCLKS/2
9
0111: LCDCLKS/2
10
1000: LCDCLKS/2
11
1001: LCDCLKS/2
12
1010-1111: Setting prohibited
2-0 LCCKS2-0
LCDCLKS selection
000: SCLK (Low-speed clock)
001: HCLK (High-speed clock) /2
4
010: HCLK (High-speed clock) /2
5
011: HCLK (High-speed clock) /2
6
100: HCLK (High-speed clock) /2
7
101: HCLK (High-speed clock) /2
8
110-111: Setting prohibited
bp 76543210
Bit name Reserved LCUPMD
At reset00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
bp Bit name Description
7-1 Reserved Must be set to "0".
0LCUPMD
BSTVOL boost voltage selection
0: Three times voltage boost
1: Two times voltage boost