Chapter 17
LCD
XVII - 16 Control Registers
Segment Output Latch (LCDATA0-42: 0x03E90-0x03EBA)
A 8-bit segment output latch (LCDATAn) is assigned for each segment. Each bit is read in synchronization with
the COMn timing and is output from the SEGn. LCDATAn can be read or written like RAM, and the values of
them are not valid at reset.
Figure:17.2.1 shows the relation of segment output latch and segment/common pins. these differ in each product.
Figure:17.2.1 Correspondence of segment output latch and segment / common pins
↓
bit7
↓
bit6
↓
bit5
↓
bit4
↓
bit3
↓
bit2
↓
bit1
↓
bit0
CDATA0 0x3E90 → SEG0
MN101L
R05D
CDATA1 0x3E91 → SEG1
CDATA2 0x3E92 → SEG2
CDATA3 0x3E93 → SEG3
CDATA4 0x3E94 → SEG4
CDATA5 0x3E95 → SEG5
CDATA6 0x3E96 → SEG6
CDATA7 0x3E97 → SEG7
CDATA8 0x3E98 → SEG8
CDATA9 0x3E99 → SEG9
CDATA10 0x3E9A → SEG10
CDATA11 0x3E9B → SEG11
CDATA12 0x3E9C → SEG12
CDATA13 0x3E9D → SEG13
CDATA14 0x3E9E → SEG14
CDATA15 0x3E9F → SEG15
CDATA16 0x3EA0 → SEG16
CDATA17 0x3EA1 → SEG17
CDATA18 0x3EA2 → SEG18
CDATA19 0x3EA3 → SEG19
CDATA20 0x3EA4 → SEG20
CDATA21 0x3EA5 → SEG21
CDATA22 0x3EA6 → SEG22
CDATA23 0x3EA7 → SEG23
CDATA24 0x3EA8 → SEG24
CDATA25 0x3EA9 → SEG25
CDATA26 0x3EAA → SEG26
CDATA27 0x3EAB → SEG27
CDATA28 0x3EAC → SEG28
CDATA29 0x3EAD → SEG29
CDATA30 0x3EAE → SEG30
CDATA31 0x3EAF → SEG31
CDATA32 0x3EB0 → SEG32
CDATA33 0x3EB1 → SEG33
CDATA34 0x3EB2 → SEG34
CDATA35 0x3EB3 → SEG35
CDATA36 0x3EB4 → SEG36
CDATA37 0x3EB5 → SEG37
CDATA38 0x3EB6 → SEG38
CDATA39 0x3EB7 → SEG39
CDATA40 0x3EB8 → SEG40
CDATA41 0x3EB9 → SEG41
CDATA42 0x3EBA → SEG42
SEG0
MN101L
R04D
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
MN101
R03D
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG1
SEG1
SEG1
SEG1
SEG1
SEG1
SEG1
SEG1
SEG1
SEG1
SEG2
Register
Address
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