Panasonic MN101L Series

Chapter 20
Appendix
XX - 10 Instruction set
..
Other than the instruction of MN101L Series, the assembler of this Series has the following
instructions as macro instructions.
The assembler will interpret the macro instructions below as the assembler instructions.
..
Mnemonic
*1
*2
1
1111
0000
0000
0000
0001
0010
0011
2
1110
0001
0011
0000
1rep
0000
0000
3
<t4>
4
5
678
910
11Ext.
0010
0010
0010
{
3
2
2
2
3
3
3
max(6+d+3i,
6+2d+2i)
max(4+2d+i,
6+2d)
max(5+3d+i,
6+3d)
1
1
2
2
SP-3 → SP, (PC+3).bp7~0 → mem8(SP),
(PC+3).bp15~8 → mem8(SP+1),
(PC+3).H → mem8(SP+2).bp7,
0 → mem8(SP+2).bp6~4,
(PC+3).bp19~16 → mem8(SP+2).bp3~0,
mem8(x'04080'+tbl4<<2) → PC.bp7~0,
mem8(x'04080'+tbl4<<2+1) →
PC.bp15~8,
mem8(x'04080'+tbl4<<2+2).bp7 → PC.H,
mem8(x'04080'+tbl4<<2+2).bp3~0 →
PC.bp19~16
mem8(SP) → (PC).bp7~0,
mem8(SP+1) → (PC).bp15~8,
mem8(SP+2).bp7 → (PC).H,
mem8(SP+2).bp3~0 → (PC).bp19~16,
SP+3 → SP
mem8(SP) → PSW,
mem8(SP+1) → (PC).bp7~0,
mem8(SP+2) → (PC).bp15~8,
mem8(SP+3).bp7 → (PC).H,
mem8(SP+3).bp3~0 → (PC).bp19~16,
mem8(SP+4) → HA-l,
mem8(SP+5) → HA-h,
SP+6 → SP
PC+2 → PC
imm3-1 → RPC
PSW & x'3F' → PSW
PSW | x'C0' → PSW
JSRV (tbl4)
RTS
RTI
NOP
REP imm3
BE
BD
-
-
z
-
-
-
-
-
-
z
-
-
-
-
-
-
z
-
-
-
-
-
-
z
-
-
-
-
JSR
RTS
RTI
NOP
REP
BE
BD
Group REP NotesOperation
VF NF CF ZF
Code
Size
Execution
Cycle
Machine Code
MN101L SERIES INSTRUCTION SET
Flag
*1 When the value of SP is odd number, the execution cycle is added "(1+d)".
*2 imm3 = 1 : repeat count = 0 (rep : imm3 - 1)
NOP Instruction
Control Instructions
macro instructions
INC
DEC
INC
DEC
INC2
DEC2
CLR
ASL
LSL
ROL
NEG
NOPL
MOV
MOV
MOVW
MOVW
MOVW
MOVW
Dn
Dn
An
An
An
An
Dn
Dn
Dn
Dn
Dn
(SP), Dm
Dn, (SP)
(SP), DWm
DWn, (SP)
(SP), Am
An, (SP)
ADD
ADD
ADDW
ADDW
ADDW
ADDW
SUB
ADD
ADD
ADDC
NOT
ADD
MOVW
MOV
MOV
MOVW
MOVW
MOVW
MOVW
n = m
n = m
n = m
n = m
n = m
1, Dm
-1, Dm
1, Am
-1, Am
2, Am
-2, Am
Dn, Dm
Dn, Dm
Dn, Dm
Dn, Dm
Dn
1, Dm
DWn, DWm
(0, SP), Dm
Dn, (0, SP)
(0, SP), DWm
DWn, (0, SP)
(0, SP), Am
An, (0, SP)
replaced instructions remarks