Panasonic MN101L Series

Chapter 2
CPU
Reset II - 31
 Oscillation Stabilization Wait Time Control Register (DLYCTR: 0x03F03)
..
The stabilization wait cycle of external oscillation should be determined in consultation with
the oscillator manufacturer.
..
..
Set the stabilization wait cycle of internal oscillation to match the following conditions.
- Internal high-speed oscillation: 15 µs or more
- Internal low-speed oscillation: 100 µs or more
..
bp 76543210
Bit name---- DLY3-0
At reset00000000
AccessRRRRR/WR/WR/WR/W
bp Bit name Description
7-4 - Always read as 0.
3-0 DLY3-0
Oscillation stabilization wait cycle selection
0000: 2
14
× (1/f
OSCSTBCLK
)
0001: 2
13
× (1/f
OSCSTBCLK
)
0010: 2
12
× (1/f
OSCSTBCLK
)
0011: 2
11
× (1/f
OSCSTBCLK
)
0100: 2
10
× (1/f
OSCSTBCLK
)
0101: 2
9
× (1/f
OSCSTBCLK
)
0110: 2
8
× (1/f
OSCSTBCLK
)
0111: 2
7
× (1/f
OSCSTBCLK
)
1000: 2
6
× (1/f
OSCSTBCLK
)
1001: 2
5
× (1/f
OSCSTBCLK
)
1010: 2
4
× (1/f
OSCSTBCLK
)
1011: 2
3
× (1/f
OSCSTBCLK
)
1100: 2
2
× (1/f
OSCSTBCLK
)
1101: Prohibited
1110: Prohibited
1111: Prohibited