Samsung S3F84B8 - TACON - Timer a Control Register: E1 H, BANK1

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS
4-36
4.1.39 TACON — TIMER A CONTROL REGISTER: E1H, BANK1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
0 0 0 0 0 0 0 0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
Timer A Operating Mode Selection Bits
0 0 Internal mode (TAOUT mode)
0 1 Capture mode (captures on rising edge; counter running; OVF can occur)
1 0 Capture mode (captures on falling edge; counter running; OVF can occur)
.7–.6
1 1 PWM mode (OVF interrupt can occur)
Timer A Counter Clear Bit
0 No effect.
.5
1 Clears the timer A counter (After clearing, returns to zero).
Timer A Start/Stop Bit
0 Stops Timer A.
.4
1 Starts Timer A.
Timer A Match/Capture Interrupt Enable Bit
0 Disables interrupt.
.3
1 Enables interrupt.
Timer A Overflow Interrupt Enable Bit
0 Disables interrupt.
.2
1 Enables interrupt.
Timer A Match Interrupt Pending Bit
0 No interrupt is pending; clears pending bit (when write).
.1
1 Interrupt is pending.
Timer A Overflow Interrupt Pending Bit
0 No interrupt is pending; clears pending bit (when write).
.0
1 Interrupt is pending.