Samsung S3F84B8 - CMP1 CON - Comparator1 Control Register: EBH, BANK0

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS
4-10
4.1.7 CMP1CON — COMPARATOR1 CONTROL REGISTER: EBH, BANK0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
0 0 0 0 0 0 1 0
Read/Write
R/W R/W R/W R/W R/W R/W R R/W
Comparator 1 Reference Level Selection Bit
0 0 0 0.45VDD
0 0 1 0.50VDD
0 1 0 0.55VDD
0 1 1 0.60VDD
1 0 0 0.65VDD
1 0 1 0.70VDD
1 1 0 0.75VDD
.7–.5
1 1 1 0.80VDD
Comparator1 Output Polarity Select Bit
0 Does not invert CMP1 output.
.4
1 Inverts CMP1 output.
Comparator1 Enable Bit
0 Disables CMP1.
.3
1 Enables CMP1.
Comparator1 Interrupt Enable Bit
0 Disables CMP1 interrupt.
.2
1 Enables CMP1 interrupt.
Comparator1 Status Bit
0 CMP1_N > CMP1_P
.1
1 CMP1_N < CMP1_P
Comparator1 Pending Bit
0 No interrupt is pending (clears pending bit when write).
.0
1 CMP1 interrupt is pending.
NOTE:
1. Polarity selection bit (CMP1CON.4) will not affect the interrupt generation logic.
2. Refer to “Programming Tip” in Chapter 14 for proper configuration sequence.