Samsung S3F84B8 - Control Registers

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS
4-1
4 CONTROL REGISTERS
4.1 OVERVIEW OF CONTROL REGISTERS
This section provides a detailed description of the S3F84B8 control registers in an easy-to-read format to
familiarize you with the mapped locations in register file. You can also use them as a quick-reference source when
writing application programs.
Table 4-1
summarizes the system and peripheral registers. In addition, Figure 4-1 illustrates the important
features of standard register description format.
Control register descriptions are arranged in alphabetical order according to the register mnemonic. More
information about control registers is presented in the context of various peripheral hardware descriptions in Part II
of this manual.
Table 4-1 System and Peripheral Control Registers Set1 Bank0
Address and
Location
RESET Value (Bit) Register Name Mnemonic
Address R/W 7 6 5 4 3 2 1 0
Locations D0-D2H are not mapped
Basic Timer Control Register BTCON D3H R/W 0 0 0 0 0 0 0 0
Clock Control Register CLKCON D4H R/W 0 – – 0 0 – – –
System Flags Register FLAGS D5H R/W x x x x x x 0 0
Register Pointer 0 RP0 D6H R/W 1 1 0 0 0 – – –
Register Pointer 1 RP1 D7H R/W 1 1 0 0 1 – – –
Location D8H is not mapped
Stack Pointer register SPL D9H R/W x x x x x x x x
Instruction Pointer (High Byte) IPH DAH R/W x x x x x x x x
Instruction Pointer (Low Byte) IPL DBH R/W x x x x x x x x
Interrupt Request register IRQ DCH R 0 0 0 0 0 0 0 0
Interrupt Mask Register IMR DDH R/W x x x x x x x x
System Mode Register SYM DEH R/W 0 – – x x x 0 0
Register Page Pointer PP DFH R/W 0 0 0 0 0 0 0 0
Port 0 data register P0 E0H R/W – 0 0 0 0 0 0 0
Port 1 data register P1 E1H R/W – – – – – 0 0 0
Port 2 data register P2 E2H R/W 0 0 0 0 0 0 0 0
Port 0 interrupt control register P0INT E3H R/W – 0 0 0 0 – 0 0
Port 0 control register (High byte) P0CONH E4H R/W – – 0 0 0 0 0 0