Samsung S3F84B8 - Figure 9-2 Port 0 Control Register Low Byte (P0 CONL)

S3F84B8_UM_REV 1.00 9 I/O PORTS
9-4
Port 0 Low Control Register (P0CONL)
E4H, Set1, Bank0, R/W, Reset value:00H
LSBMSB.7.6.5.4.3.2.1.0
.5 .4 bit Not used for S 3F84B8
P0.1
/INT1
P0.0
/INT0
.3 .2 bit/P0.1/INT1
00
01
10
11
Input mode/INT1 falling edge interrupt
Input mode with pull-up; INT1 falling edge interrupt
Push-pull output
Open-drain output
.7 -.6 bit/P0.3/INT2/BUZ
00
01
10
11
Input mode/INT2 falling edge interrupt
Input mode with pull up /INT2 falling edge interrupt
Push-pull output
Alternative function: BUZ output
.1 .0 bit/P0.0/INT0
00
01
10
11
Input mode/INT0 falling edge interrupt
Input mode with pull-up; INT0 falling edge interrupt
Push-pull output
Open-drain output
P0.3
/INT2
/BUZ
Not Used
NOTE: P1.2 could be used as either nRESET pin or normal input pin .
Figure 9-2 Port 0 Control Register Low Byte (P0CONL)