Samsung S3F84B8 - BITC - Bit Complement

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET
6-18
6.3.6 BITC — BIT COMPLEMENT
BITC dst.b
Operation: dst(b)  NOT dst(b)
This instruction complements the specified bit within the destination without affecting any other
bits there.
Flags: C: Unaffected.
Z: Set if the result is “0”; cleared otherwise.
S: Cleared to “0”.
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode
dst
opc dst | b | 0 2 4 57 rb
NOTE: In the second byte of instruction format, the destination address is four bits, the bit address ‘b’ is three bits,
and the LSB address value is one bit in length.
Example: Given R1 = 07H:
BITC R1.1  R1 = 05H
If working register R1 contains the value 07H (00000111B), the statement “BITC R1.1”
complements bit one of the destination and leaves the value 05H (00000101B) in register R1.
Since the result of complement is not “0”, the zero flag (Z) in FLAGS register (0D5H) is cleared.