Samsung S3F84B8 - CMP0 CON - Comparator0 Control Register: EAH, BANK0

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS
4-9
4.1.6 CMP0CON — COMPARATOR0 CONTROL REGISTER: EAH, BANK0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
– – – 0 0 0 1 0
Read/Write
– – – R/W R/W R/W R R/W
.7–.5 Not used for S3F84B8.
Comparator0 Output Polarity Select Bit
(1)
0 Does not invert CMP0 output.
.4
1 Inverts CMP0 output.
Comparator0 Enable Bit
(2)
0 Disables CMP0.
.3
1 Enables CMP0.
Comparator0 Interrupt Enable Bit
0 Disables CMP0 interrupt.
.2
1 Enables CMP0 interrupt.
Comparator0 Status Bit
0 CMP0_N > CMP0_P
.1
1 CMP0_N < CMP0_P
Comparator0 Pending Bit
0 No interrupt is pending (clears pending bit when write).
.0
1 CMP0 interrupt is pending.
NOTE:
1. Polarity selection bit (CMP0CON.4) will not affect the interrupt generation logic.
2. Refer to “Programming Tip” in Chapter 14 for proper configuration sequence.