Samsung S3F84B8 - CMP2 CON - Comparator1 Control Register: ECH, BANK0

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS
4-11
4.1.8 CMP2CON — COMPARATOR1 CONTROL REGISTER: ECH, BANK0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value
0 0 0 0 0 0 1 0
Read/Write
R/W R/W R/W R/W R/W R/W R R/W
Comparator 2 Reference Level Selection Bit
0 0 0 0.45VDD
0 0 1 0.50VDD
0 1 0 0.55VDD
0 1 1 0.60VDD
1 0 0 0.65VDD
1 0 1 0.70VDD
1 1 0 0.75VDD
.7–.5
1 1 1 0.80VDD
Comparator2 Output Polarity Select Bit
0 Does not invert CMP2 output.
.4
1 Inverts CMP2 output.
Comparator2 Enable Bit
0 Disables CMP1.
.3
1 Enables CMP1.
Comparator2 Interrupt Enable Bit
0 Disables CMP1 interrupt.
.2
1 Enables CMP1 interrupt.
Comparator2 Status Bit
0 CMP2_N > CMP2_P
.1
1 CMP2_N < CMP2_P
Comparator2 Pending Bit
0 No interrupt is pending (clears pending bit when write).
.0
1 CMP2 interrupt is pending.
NOTE:
1. Polarity selection bit (CMP2CON.4) will not affect the interrupt generation logic.
2. Refer to “Programming Tip” in Chapter 14 for proper configuration sequence.