Samsung S3F84B8 - IMR - Interrupt Mask Register

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS
4-17
4.1.16 IMR — INTERRUPT MASK REGISTER: DDH, BANK0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
x x x x x x x x
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
Interrupt Level 7 (IRQ7)
0 Disables (mask).
.7
1 Enables (unmask).
Interrupt Level 6 (IRQ6)
0 Disables (mask).
.6
1 Enables (unmask).
Interrupt Level 5 (IRQ5)
0 Disables (mask).
.5
1 Enables (unmask).
Interrupt Level 4 (IRQ4)
0 Disables (mask).
.4
1 Enables (unmask).
Interrupt Level 3 (IRQ3)
0 Disables (mask).
.3
1 Enables (unmask).
Interrupt Level 2 (IRQ2)
0 Disables (mask).
.2
1 Enables (unmask).
Interrupt Level 1 (IRQ1)
0 Disables (mask).
.1
1 Enables (unmask).
Interrupt Level 0 (IRQ0)
0 Disables (mask).
.0
1 Enables (unmask).
NOTE: When an interrupt level is masked, the CPU does not recognize any interrupt requests that are issued.