S3F84B8_UM_REV 1.00 2 ADDRESS SPACES
2-6
2.3.1 REGISTER PAGE POINTER (PP)
The S3F8 series architecture supports the logical expansion of physical 256 byte internal register file (using an 8-
bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the
register page pointer (PP, DFH).
After reset, the page pointer’s source value (lower nibble) and the destination value (upper nibble) are always
“0000”, automatically selecting page 0 as the source and destination page for register addressing.
Register Page Pointer (PP)
DFH, Set 1, R/W
LSBMSB .7 .6 .5 .4 .3 .2 .1 .0
Destination register page selection bits:
NOTE: A hardware reset operation writes the 4-bit destination and source values shown above to the
register page pointer.
These values should be modified to address other pages.
Not used for the S3F84B8
Source register page selection bits:
Not used for the S3F84B8
Figure 2-4 Register Page Pointer (PP)
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