S3F84B8_UM_REV 1.00 6 INSTRUCTION SET
6-77
6.3.65 SRA — SHIFT RIGHT ARITHMETIC
SRA dst
Operation: dst (7) dst (7)
C dst (0)
dst (n) dst (n + 1), n = 0–6
An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit
position 6.
70
C
6
Flags: C: Set if the bit shifted from the LSB position (bit zero) is “1”.
Z: Set if the result is “0”; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Always cleared to “0”.
D: Unaffected.
H: Unaffected.
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode
dst
opc dst 2 4 D0 R
4 D1 IR
Examples: Given register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = “1”:
SRA 00H Register 00H = 0CD, C = “0”
SRA @02H Register 02H = 03H, register 03H = 0DEH, C = “0”
In the first example, if general register 00H contains the value 9AH (10011010B), the statement
“SRA 00H” shifts the bit values in register 00H right one bit position. Bit zero (“0”) clears the C
flag and bit 7 (“1”) is then shifted to bit 6 position (bit 7 remains unchanged). This leaves the value
0CDH (11001101B) in destination register 00H.
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