S3F84B8_UM_REV 1.00 12 TIMER 0
12-8
Timer B Control Register (TDCON)
E9H, Set1, Bank1, Reset = 00H, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Timer D counter clear bit:
0 = No effect
1 = Clear the timer D counter
(when write)
Timer D operating mode selection bits:
00 = Interval mode
01 = 6-bit PWM mode (OVF interrupt can occur)
10 = 7-bit PWM mode (OVF interrupt can occur)
11 = 8-bit PWM mode (OVF interrupt can occur)
Timer D overflow interrupt pending bit
0 = no interrupt pending
(clear pending bit when write)
1 = interrupt pending
Timer D match interrupt pending bit
0 = no interrupt pending
(clear pending bit when write)
1 = interrupt pending
Timer D match interrupt enable bit:
0 = Disable match interrupt
1 = Enable match interrupt
Timer D overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer D count enable bit:
0 = Disable counting operating
1 = Enable counting operating
Figure 12-7 Timer D Control Register (TDCON)
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