Samsung S3F84B8 - Page 265

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S3F84B8_UM_REV 1.00 14 COMPARATOR

14-7

14.1.1.2.2 Block Diagram of Comparator 1/2/3

C1/2/3PLR (CMP1/2/3CON.4)

C1/2/3EN (CMP1/2/ 3CON.3)

PWM

CMP0_N

CMP1/2/3

SET

CLR

Interrupt

Fosc

CMP1/2/3CON.1

INT Enable (CMP1/2/3CON.2)

CMP1/2/3CON.7-.5

MUX

0.45 VDD

0. 50 VDD

0. 80 VDD

...

CMPINT.3-.2/.5-.4/.7-.6

INT

CTRL

CMP1/2/3CON.0

NOTE:

1. Polarity selection bit (CMP1/2/3CON.4) will not affect interrupt generation logic .

2. PWM lock signal is falling edge active only .

Figure 14-8 Block Diagram of Comparator 1/2/3

Example 14-1 Comparator Configuration



LD CMPINT, #055H ; Falling edge interrupt

AND CMP0/1/2/3CON, #0FEH ; Must clear the pending bit before enabling CMP

LD CMP0/1/2/3CON, #0CH ; Enables CMP, enables interrupt



Main Page

Overview of S3F84B8 Microcontroller18
Key Features of S3F84B819
Block Diagram of S3F84B822
Pin Assignments23
Pin Descriptions24
Table 1-2 Pin Descriptions Used to Read/Write the Flash ROM25
Pin Circuits26
Figure 1-5 Pin Circuit Type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7)27
Address Spaces31
Internal Program Memory (ROM)32
Smart Option33
Register Architecture34
Figure 2-3 Internal Register File Organization in S3F84B835
Register Page Pointer (PP)36
Register Set 137
Prime Register Space38
Working Registers39
Using the Register Points (RP)40
Figure 2-8 Non-Contiguous 16 Byte Working Register Block41
Register Addressing42
Common Working Register Area (C0H–CFH)44
Bit Working Register Addressing45
Figure 2-13 4-Bit Working Register Addressing Example46
Bit Working Register Addressing47
Figure 2-15 8-Bit Working Register Addressing Example48
System and User Stack49
Addressing Modes51
Register (R) Addressing Mode52
Indirect Register (IR) Addressing Mode53
Indirect Register (IR) Addressing Mode (Continued)54
Indirect Register (IR) Addressing Mode (Continued)55
Indirect Register (IR) Addressing Mode (Concluded)56
Indexed (X) Addressing Mode57
Indexed (X) Addressing Mode (Continued)58
Indexed (X) Addressing Mode (Concluded)59
Direct Address (DA) Mode60
Direct Address (DA) Mode (Continued)61
Indirect Address (IA) Mode62
Relative Address (RA) Mode63
Immediate Mode (IM)64
Control Registers65
ADCON — A/D Converter Control Register: FAH, BANK069
AMTDATA — Anti-Mis-Trigger Data Register: F6H, BANK070
BUZCON — BUZ Control Register: F7H, BANK071
CLKCON — Clock Control Register: D4H, BANK072
CMP0CON — Comparator0 Control Register: EAH, BANK073
CMP1CON — Comparator1 Control Register: EBH, BANK074
CMP2CON — Comparator1 Control Register: ECH, BANK075
CMP3CON — Comparator1 Control Register: EDH, BANK076
CMPINT — Comparator Interrupt Mode Control Register: EEH, BANK077
FLAGS — System Flags Register: D5H, BANK078
FMCON — Flash Memory Control Register: F5H, BANK179
FMSECL — Flash Memory Sector Address Register (Low Byte): F8H, BANK180
IMR — Interrupt Mask Register: DDH, BANK081
IPH — Instruction Pointer (High Byte): DAH, BANK082
IPR — Interrupt Priority Register: FFH, BANK083
IRQ — Interrupt Request Register: DCH, BANK084
OPACON — OP AMP Control Register: E0H, BANK185
P0CONH — Port 0 Control Register (High Byte): E4H, Bank086
P0CONL — Port 0 Control Register (Low Byte): E5H, BANK087
P0INT — Port 0 Interrupt Control Register: E3H, BANK088
P0PND — Port 0 Interrupt Pending Register: E6H, BANK089
P1CON — Port 1 Control Register: E7H, BANK090
P2CONH — Port 2 Control Register (High Byte): E8H, BANK091
P2CONL — Port 2 Control Register (Low Byte): E9H, BANK092
PWMCON — PWM Control Register: EFH, BANK093
PWMCCON — PWM CMP Control Register: F0H, BANK094
PWMDL — Comparator0 Output Delay Register: F5H, Bank095
RESETID — Reset Source Indicating Register: F2H, BANK196
RP0 — Register Pointer 0: D6H, BANK097
SPL — Stack Pointer: D9H, BANK098
SYM — System Mode Register: DEH, BANK099
TACON — Timer a Control Register: E1H, BANK1100
TAPS — TA Pre-Scalar Register: E2H, BANK1101
TCCON — Timer C Control Register: E5H, BANK1102
TCPS — TC Pre-Scalar Register: E6H, BANK1103
TDCON — Timer D Control Register: E9H, BANK1104
TDPS — TD Pre-Scalar Register: EAH, BANK1105
Interrupt Structure106
Interrupt Types107
S3F84B8 Interrupt Structure108
Interrupt Vector Addresses109
System-Level Interrupt Control Registers110
Interrupt Processing Control Points111
Peripheral Interrupt Control Registers112
System Mode Register (SYM)113
Interrupt Mask Register (IMR)114
Interrupt Priority Register (IPR)115
Interrupt Request Register (IRQ)117
Interrupt Pending Function Types118
Interrupt Source Polling Sequence119
Generating Interrupt Vector Addresses120
Instruction Pointer (IP)121
Procedure for Initiating Fast Interrupts122
Instruction Set123
Flags Register (FLAGS)127
Flag Descriptions128
Instruction Set Notation129
Table 6-4 Instruction Notation Conventions130
Table 6-5 Opcode Quick Reference131
Condition Codes133
Instruction Descriptions134
ADC — Add with Carry135
ADD — Add136
AND — Logical and137
BAND — Bit and138
BCP — Bit Compare139
BITC — Bit Complement140
BITR — Bit Reset141
BITS — Bit Set142
BOR — Bit or143
BTJRF — Bit Test, Jump Relative on False144
BTJRT — Bit Test, Jump Relative on True145
BXOR — Bit XOR146
CALL — Call Procedure147
CCF — Complement Carry Flag148
CLR — Clear149
COM — Complement150
CP — Compare151
CPIJE — Compare, Increment, and Jump on Equal152
CPIJNE — Compare, Increment, and Jump on Non-Equal153
DA — Decimal Adjust154
DA — Decimal Adjust (Continued)155
DEC — Decrement156
DECW — Decrement Word157
DI — Disable Interrupts158
DIV — Divide (Unsigned)159
DJNZ — Decrement and Jump if Non-Zero160
EI — Enable Interrupts161
ENTER — Enter162
Figure 6-3 Example of the Usage of EXIT Statement163
IDLE — Idle Operation164
INC — Increment165
INCW — Increment Word166
IRET — Interrupt Return167
JP — Jump168
JR — Jump Relative169
LD — Load170
LD — Load (Continued)171
LDB — Load Bit172
LDC/LDE — Load Memory173
LDC/LDE — Load Memory (Continued)174
LDCD/LDED — Load Memory and Decrement175
LDCI/LDEI — Load Memory and Increment176
LDCPD/LDEPD — Load Memory with Pre-Decrement177
LDCPI/LDEPI — Load Memory with Pre-Increment178
LDW — Load Word179
MULT — Multiply (Unsigned)180
NEXT — Next181
NOP — no Operation182
OR — Logical or183
POP — Pop from Stack184
POPUD — Pop User Stack (Decrementing)185
POPUI — Pop User Stack (Incrementing)186
PUSH — Push to Stack187
PUSHUD — Push User Stack (Decrementing)188
PUSHUI — Push User Stack (Incrementing)189
RCF — Reset Carry Flag190
RET — Return191
RL — Rotate Left192
RLC — Rotate Left through Carry193
RR — Rotate Right194
RRC — Rotate Right through Carry195
SB0 — Select Bank 0196
SBC — Subtract with Carry197
SCF — Set Carry Flag198
SRA — Shift Right Arithmetic199
RP/SRP0/SRP1 — Set Register Pointer200
STOP — Stop Operation201
SUB — Subtract202
SWAP — Swap Nibbles203
TCM — Test Complement under Mask204
TM — Test under Mask205
WFI — Wait for Interrupt206
XOR — Logical Exclusive or207
Clock Circuit208
Clock Status During Power-Down Modes209
Reset and Power-Down211
MCU Initialization Sequence213
Power-Down Modes214
Idle Mode215
Hardware Reset Values216
I/O Port219
Port 0220
Figure 9-1 Port 0 Control Register High Byte (P0CONH)221
Figure 9-2 Port 0 Control Register Low Byte (P0CONL)222
Figure 9-3 Port 0 Interrupt Control Register (P0INT)223
Figure 9-4 Port 0 Interrupt Pending Register (P0PND)224
Port 1225
Port 2227
Figure 9-6 Port 2 High-Byte Control Register (P2CONH)228
Figure 9-7 Port 2 Low-Byte Control Register (P2CONL)229
Basic Timer230
Basic Timer Control Register (BTCON)231
Basic Timer Function Description232
Figure 10-2 Oscillation Stabilization Time on RESET233
Figure 10-3 Oscillation Stabilization Time on STOP Mode Release234
Bit Timer a236
Functional Description237
Timer a Control Register (TACON)238
Block Diagram of Timer a241
Timer242
Functional Description of One 16-Bit Timer Mode (Timer 0)243
Block Diagram of Timer 0245
Two 8-Bit Timers Mode (Timer C and D)246
Figure 12-5 Timer C Prescaler Register (TCPS)248
Functional Description of Two 8-Bit Timers Mode (Timer C and D)250
Figure 12-8 Timers C and D Function Block Diagram251
Pulse Width Modulation Mode (Timer D)252
A/D Converter253
Using A/D Pins for Standard Digital Input254
Internal Reference Voltage Levels255
Conversion Timing257
Comparator259
Figure 14-2 CMP Interrupt Mode Control Register (CMPINT)260
Comparator 1/2/3262
Figure 14-7 CMP Interrupt Mode Control Register (CMPINT)264
Operational Amplifier266
OPAMP Control Register267
Reference Circuit268
Bit Ih-Pwm269
Functional Description of 10-Bit IH-PWM270
PWM Functional Description271
PWM Control Register (PWMCON)272
PWM CMP Linkage Control Register (PWMCCON)273
Block Diagram of PWM Module274
Figure 16-6 Example of the Cooperation of PWM and Comparator 0_Delay Trigger275
Programmable Buzzer277
BUZ Frequency Table (@4Mhz)278
Flash Mcu Rom280
Embedded Flash Memory Interface282
User Program Mode283
Flash Memory Control Registers (User Program Mode)284
Flash Memory Sector Address Registers285
Sector Erase286
Figure 19-7 Sector Erase Flowchart in User Program Mode287
Programming289
Figure 19-8 Byte Program Flowchart in a User Program Mode290
Figure 19-9 Program Flowchart in a User Program Mode291
Reading295
Hard Lock Protection296
Low Voltage Reset297
Electrical Data299
Table 21-1 Absolute Maximum Ratings300
Figure 21-2 Operating Voltage Range @ External Clock305
Figure 21-4 Stop Mode Release Timing When Initiated by a RESET306
Table 21-7 A/D Converter Electrical Characteristics307
Table 21-8 OP AMP Electrical Characteristics308
Table 21-11 Flash Memory AC Electrical Characteristics309
Figure 21-6 Circuit Diagram to Improve the EFT Characteristics310
Development Tools311
Development System Configuration312
TB84B8 Target Board313
Figure 22-5 S3F84B8 Probe Adapter for 20-DIP Package317
Third Parties for Development Tools318
OTP/MTP Programmer (Writer)319
Mechanical Data321

Samsung S3F84B8 - Page 265

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