Schweitzer Engineering Laboratories SEL-787 - Figure 4.47 Logic Diagram of a Latch Switch; Table 4.26 Latch Bits Equation Settings

4.73
Date Code 20081022 Instruction Manual SEL-787 Relay
Protection and Logic Functions
Logic Settings (SET L Command)
Figure 4.47 Logic Diagram of a Latch Switch
If setting SETn asserts to logical 1, latch bit LTn asserts to logical 1. If setting
RSTn asserts to logical 1, latch bit LTn deasserts to logical 0. If both settings
SETn and RSTn assert to logical 1, setting RSTn has priority and latch bit LTn
deasserts to logical 0. You can use these latch bits in SEL
OGIC control
equations to create custom logic for your application.
The SEL-787 includes 32 latches. Table 4.26 shows the SET and RESET
default settings for Latch 1 through Latch 4. The remaining latches are all set
to NA.
Latch Bits:
Nonvolatile State
Power Loss
The states of the latch bits (LT01–LT32) are retained if power to the device is
lost and then restored. If a latch bit is asserted (e.g., LT02 := logical 1) when
power is lost, it is asserted (LT02 := logical 1) when power is restored. If a
latch bit is deasserted (e.g., LT03 := logical 0) when power is lost, it is
deasserted (LT03 := logical 0) when power is restored.
Table 4.26 Latch Bits Equation Settings
Settings Prompt Setting Range Setting Name := Factory Default
SET01 SELOGIC SET01 := R_TRIG SV01T AND NOT LT01
RST01 SEL
OGIC RST01 := R_TRIG SV01T AND LT01
SET02 SEL
OGIC SET02 := R_TRIG SV02T AND NOT LT02
AND PB02
RST02 SEL
OGIC RST02 := R_TRIG SV02T AND LT02 AND
PB02
SET03 SEL
OGIC SET03 := (PB03 AND R_TRIG SV02T)
AND LT01 AND NOT (52A1 AND NOT
LT02 OR 52A2 AND LT02)
RST03 SELOGIC RST03 := (R_TRIG SV02T OR SV03T)
AND LT03
SET04 SEL
OGIC SET04 := (PB04 AND R_TRIG SV02T)
AND (52A1 AND NOT LT02 OR 52A2
AND LT02)
RST04 SEL
OGIC RST04 := (R_TRIG SV02T OR SV04T)
AND LT04
•
•
•
•
•
•
•
•
•
SET32 SEL
OGIC SET32 := NA
RST32 SEL
OGIC RST32 := NA
LTn
SETn
RSTn
(Set)
(Reset)
(n = 01 throu
g
h 32)
Relay
Word
Bits
SELOGIC
Setting