J.7
Date Code 20081022 Instruction Manual SEL-787 Relay
Relay Word Bits
Definitions
87HB Harmonic block differential element asserted. 16
87HR Harmonic restrained element (HR1 OR HR2 OR HR3).
b
16
87HR1 Harmonic restrained element 1. 16
87HR2 Harmonic restrained element 2. 16
87HR3 Harmonic restrained element 3. 16
87R Restrained differential element Trip (87HR OR 87HB). 5
87R1 Restrained differential element 1 (not considering harmonic blocks). 5
87R2 Restrained differential element 2 (not considering harmonic blocks). 5
87R3 Restrained differential element 3 (not considering harmonic blocks). 5
87U Unrestrained differential element Trip (87U1 OR 87U2 OR 87U3). 5
87U1 Unrestrained differential element 1 Trip. 5
87U2 Unrestrained differential element 2 Trip. 5
87U3 Unrestrained differential element 3 Trip. 5
AIHAL Analog inputs High Alarm Limit. If any AInnnHAL = 1, then AIHAL = 1. 91
AIHW1 Analog inputs High Warning, Level 1. If any AinnnHW1 = 1, then AIHW1 = 1. 91
AIHW2 Analog inputs High Warning, Level 2. If any AinnnHW2 = 1, then AIHW2 = 1. 91
AILAL Analog inputs Low Alarm Limit.If any AInnnLAL=1, then AILAL=1. 91
AILW1 Analog inputs Low Warning, Level 1. If any AinnnLW1 = 1, then AILW1 = 1. 91
AILW2 Analog inputs Low Warning, Level 2.If any AinnnLW2 = 1, then AILW2 = 1. 91
AInnnHAL Analog inputs 301–504 Warnings/Alarms (where nnn = 301–504) High Alarm Limit. 92-103
AInnnHW1 Analog inputs 301–504 Warnings/Alarms (where nnn = 301–504) High Warning, Level 1. 92-103
AInnnHW2 Analog inputs 301–504 Warnings/Alarms (where nnn = 301–504) High Warning, Level 2. 92-103
AInnnLAL Analog inputs 301–504 Warnings/Alarms (where nnn = 301–504) Low Alarm Limit. 92-103
AInnnLW1 Analog inputs 301–504 Warnings/Alarms (where nnn = 301–504) Low Warning, Level 1. 92-103
AInnnLW2 Analog inputs 301–504 Warnings/Alarms (where nnn = 301–504) Low Warning, Level 2. 92-103
AMBALRM Ambient Temperature Alarm. AMBALRM asserts if the healthy ambient RTD temperature
exceeds its alarm set point.
18
AMBTRIP Ambient Temperature Trip. AMBTRIP asserts when the healthy Ambient RTD temperature
exceeds its trip set point.
18
BFI1 Breaker 1 Failure Initiation. Asserts when the SEL
OGIC control equation BFI1 results in a
logical 1. Use to indicate that the Breaker 2 Failure logic has started.
18
BFI2 Breaker 2 Failure Initiation. Asserts when the SEL
OGIC control equation BFI2 results in a
logical 1. Use to indicate that the Breaker 1 Failure logic has started.
18
BFT1 Breaker 1 Failure Trip. Asserts when the relay issues a Breaker 1 Failure trip. 7
BFT2 Breaker 2 Failure Trip. Asserts when the relay issues a Breaker 2 Failure trip. 7
CBADA Channel A, channel unavailability over threshold. 74
CBADB Channel B, channel unavailability over threshold. 74
CC1 Close command. Asserts when serial port command CC1 (CLOSE Breaker1) or front-panel or
Modbus/ DeviceNet CLOSE command is issued to Close Breaker1.
32
CC2 Close command. Asserts when serial port command CC2 (CLOSE Breaker2) or front-panel or
Modbus/ DeviceNet CLOSE command is issued to Close Breaker2.
32
CF1 Breaker 1 Close condition failure on. 32
CF2 Breaker 2 Close condition failure on. 32
Table J.2 Relay Word Bit Definitions for the SEL-787 (Sheet 4 of 9)
Bit Definition Row