Hardware Reset (RS)
3-23CPU Interrupts and Reset
3.7 Hardware Reset (RS)
When asserted, the reset input signal (RS) places the CPU into a known state.
As part of a hardware reset, all current operations are aborted, the pipeline is
flushed, and the CPU registers are reset as shown in Table 3−5. Then the
RESET interrupt vector is fetched and the corresponding interrupt service rou-
tine is executed. For the reset condition of signals, see the data sheet for your
particular C28x DSP. Also see the your data sheet for specific information on
the process for resetting your DSP. Although RS
cannot be masked, there are
some debug execution states in which RS
is not serviced (see section 7.4,
Execution Control Modes, on page 7-7).
Table 3−5. Registers After Reset
Register Bit(s) Value After Reset Comments
ACC all
00000000
16
XAR0 all 0000 0000
16
XAR1 all 0000 0000
16
XAR2 all 0000 0000
16
XAR3 all 0000 0000
16
XAR4 all 0000 0000
16
XAR5 all 0000 0000
16
XAR6 all
00000000
16
XAR7 all
00000000
16
DP all 0000
16
DP points to data page 0.
IFR 16 bits 0000
16
There are no pending
interrupts. All interrupts
pending at the time of
reset have been cleared.
IER 16 bits 0000
16
Maskable interrupts are
disabled in the IER.
DBGIER
all 0000
16
Maskable interrupts are
disabled in the DBGIER.
Note: The registers listed in this table are introduced in section 2.2, CPU Registers, on page
2-4.
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