Standard Operation for Maskable Interrupts
3-11CPU Interrupts and Reset
3.4 Standard Operation for Maskable Interrupts
The flow chart in Figure 3−4 shows the standard process for handling inter-
rupts. Section 7.4.2 on page 7-9 contains information on handling interrupts
when the DSP is in real-time mode and the CPU is halted. When more than
one interrupt is requested at the same time, the C28x services them one after
another according to their set priority ranking. See the priorities in Table 3−1
on page 3-4.
Figure 3−4 is not meant to be an exact representation of how an interrupt is
handled. It is a conceptual model of the important events.
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