Pipeline Protection
4-14
Generally, a register conflict involves one of the address registers:
- 16-bit auxiliary registers AR0−AR7
- 32-bit auxiliary registers XAR0−XAR7
- 16-bit data page pointer (DP)
- 16-bit stack pointer (SP)
Example 4−5 shows a register conflict involving auxiliary register XAR0. The
pipeline activity shown is for an unprotected pipeline, and for convenience, the
F1−D1 phases are not shown. I1 writes to XAR0 at the end of cycle 4. I2 should
not attempt to read XAR0 until cycle 5. However, I2 reads XAR0 (to generate
an address) during cycle 2. To prevent this conflict, the pipeline-protection
mechanism would hold I2 in the D2 phase for three cycles. During these
cycles, no new operations occur.
Example 4−5. Register Conflict
I1: MOVB AR0,@7 ; Load AR0 with the value addressed by
; the operand @7 and clear the upper
; half of XAR0.
I2: MOV AH,*XAR0 ; Load AH with the value pointed to by
; XAR0.
D2 R1 R2 E W Cycle
I1 1
I2 I1 2
I2 I1 3
I2 I1 4
I2 I1 5
I2 6
I2 7
You can reduce or eliminate pipeline-protection cycles due to a register conflict
by inserting other instructions between the instructions that cause the conflict.
For example, the code in Example 4−5 could be improved by moving two other
instructions from elsewhere in the program (assume that the instructions
following SETC SXM operate correctly with PM = 1 and SXM = 1):
I1: MOVB AR0,@7 ; Load AR0 with the value addressed by
; the operand @7 and clear the upper
; half of XAR0.
SPM 0 ; PM = 1 (no product shift)
SETC SXM ; SXM = 1 (sign extension on)
I2: MOV AH,*XAR0 ; Load AH with the value pointed to by
; AR0.
Inserting the SPM and SETC instructions reduces the number of pipeline-
protection cycles to one. Inserting one more instruction would remove the
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