Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT
3-8
Bits 15 and 14 of the IFR correspond to the interrupts RTOSINT and DLOGINT:
RTOSINT Real-time operating system interrupt flag
Bit 15 RTOSINT = 0 RTOSINT is not pending.
RTOSINT = 1 RTOSINT is pending.
DLOGINT Data log interrupt flag
Bit 14 DLOGINT = 0 DLOGINT is not pending.
DLOGINT = 1 DLOGINT is pending.
For bits INT1−INT14, the following general description applies:
INTx Interrupt x flag (x = 1, 2, 3, ..., or 14)
Bit (x−1) INTx = 0 INTx
is not pending.
INTx = 1 INTx
is pending.
3.3.2 CPU Interrupt Enable Register (IER) and
CPU Debug Interrupt Enable Register (DBGIER)
Figure 3−2 shows the IER. To enable an interrupt, set its corresponding bit to
1. To disable an interrupt, clear its corresponding bit to 0. Two syntaxes of the
MOV instruction allow you to read from the IER and write to the IER. In addi-
tion, the OR IER instruction enables you to set IER bits, and the AND IER
instruction enables you to clear IER bits. When a hardware interrupt is serv-
iced, or when an INTR instruction is executed, the corresponding IER bit is
cleared. At reset, all the IER bits are cleared to 0, disabling all the correspond-
ing interrupts.
Note:
When an interrupt is requested by the TRAP instruction, if the corresponding
IER bit is set, the CPU does not clear it automatically. If an application re-
quires that the IER bit be cleared, the bit must be cleared in the interrupt ser-
vice routine.
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