Analysis Breakpoints, Watchpoints, and Counter(s)
7-19Emulation Features
7.7 Analysis Breakpoints, Watchpoints, and Counter(s)
All C28x devices include two analysis units AU1 and AU2. Analysis Unit 1
(AU1) counts events or monitors address buses. Analysis Unit 2 (AU2) moni-
tors address and data buses. You can configure these two analysis units as
analysis breakpoints or watchpoints. In addition, AU1 can be configured as a
benchmark counter or event counter.
This section describes thee types of analysis features: analysis breakpoints,
watchpoints, and counters. Typical analysis unit configurations are presented
in section 7.7.4. Data logging is described in section 7.8.
7.7.1 Analysis Breakpoints
An analysis breakpoint is sometimes called a hardware breakpoint, because
it acts like a software breakpoint instruction (in this case, the ESTOP0 instruc-
tion) but does not require a modification to the application software. An analy-
sis breakpoint triggers a debug event when an instruction at a breakpoint ad-
dress would have entered the decode 2 phase of the pipeline; this halts the
CPU before the instruction is executed. A bus comparator watches the pro-
gram address bus, comparing its contents against a reference address and
a bit mask value.
Consider the following example. If a hardware breakpoint is set at T0, the CPU
stops after returning from the T1 subroutine, with the instruction counter (IC)
pointing to T0.
NOP
CALL T1
T0: MOVB AL, #0x00
SB TIMINGS, UNC
T1: NOP
RET
T2: NOP
Hardware breakpoints allow masking of address bits. For example, a hard-
ware breakpoint could be placed on the address range 00 0200
16
−00 02FF
16
by specifying the following mask address, where the eight LSBs are don’t
cares:
00 0000 0000 0010 XXXX XXXX
2
7.7.2 Watchpoints
A hardware watchpoint triggers a debug event when either an address or an
address and data match a compare value. The address portion is compared
against a reference address and bit mask, and the data portion is compared
against a reference data value and a bit mask.